layout guideline

1. bypass capacitor near pin within 2 inch if can not realize must dissguess with EE.
a. difference capacitor will
be a group if possible.
2. high speed signal need route priority.
3. clock signal to other signal space 20 mail
a. change layer need place stition via priority.
power trace route need be reserve
4. reference plane to signal spacing need to reserve priority.
1. width(1A=40mil, top or buttom can smaller to 30mil)
2. via(small via=500mA,large via=1A)
3. length
4. reference
5. impedance
6. signal via
7. 重要的訊號 優先優高於其它訊號 在取捨情況下 都要以他們為優先 例如
a. 長度 最短路徑
b. 位置 擋路的移開
8. compensation(comp)
9. feedback
10. reference voltage(vref)
11. sense
12. analog signal(CRT,AUDIO)
13. impedence(90,100,50,75,45)
14. decoupling
15. thermal pad via
16.
17. CLK termination resister
18.cal (calabreation)
19. rset

信號 資料的等長
測試程式的收集
1. 測試計劃
2. 測試程式的收集
3. 電路的收集
4. 軟體程式的收集
5. view 圖程式的規劃
6. capture
7. measure SOP
8. register
9. INTEL & AMD
10. layout viewer SOP
11. 寫測試程式
pcba 測試
1. 有無短路
2. 各個電壓
3. 各個功能
4. 訊號品質
A. 電壓時序
B. 時脈
C. 重置
5. strap
6. stress
7. burn in
8.